Lesson 2

Computer Systems Lesson 2 of 5

Inside the CPU

The fetch-decode-execute cycle we saw in Lesson 1 needs physical components to carry it out. Let's open up the processor and understand what each part is actually responsible for.

40-50 minutes Core content Core GCSE CS content FDE Visualiser + LMC

Starting point

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An Intel Core i9 processor contains around 26 billion transistors on a chip roughly the size of a fingernail. Every single transistor switches between on and off - billions of times per second. Together, they carry out one instruction at a time.

The question: What are those transistors grouped into, and what job does each group do?

The components

What is inside the CPU?

The CPU is not a single thing - it is a collection of specialised components, each with a distinct job. Click on each component below to see what it does.

Central Processing Unit (CPU)

Control Unit (CU)

Directs all CPU operations - click to learn more

Arithmetic Logic Unit (ALU)

Performs all calculations - click to learn more

Registers

Ultra-fast temporary storage - click to learn more

Cache Memory

High-speed buffer between CPU and RAM - click to learn more

Control Unit (CU)

The Control Unit is the director of the CPU. It does not process data itself - instead it coordinates every other component. During the FDE cycle, the CU:

Sends signals along the control bus to trigger memory reads and writes
Decodes instructions from the CIR to determine what operation is needed
Tells the ALU what calculation to perform
Controls the flow of data between registers

Think of it as a conductor in an orchestra - it does not play an instrument, but nothing works without it.

Arithmetic Logic Unit (ALU)

The ALU is where actual computation happens. It performs two types of operations:

Arithmetic: addition, subtraction, multiplication, division
Logic: AND, OR, NOT, XOR - comparisons and bitwise operations

The ALU receives operands from registers, performs the operation, and stores the result - typically in the Accumulator. Modern CPUs have multiple ALUs working in parallel, allowing several calculations per clock cycle.

Registers

Registers are the CPU's own private storage - tiny, extremely fast memory locations inside the processor itself. Unlike RAM, which sits outside the CPU and takes many clock cycles to access, registers can be read or written in a single clock cycle. Each has a specific purpose. See the table below for the key ones.

Cache Memory

Cache is a small amount of very fast memory built into or very close to the CPU. It stores recently or frequently used data and instructions so the processor does not have to fetch them from RAM repeatedly. Cache comes in levels - L1 (fastest, smallest, closest to the core), L2, and L3 (slower but larger). When the CPU needs data, it checks L1 first, then L2, then L3, then RAM. A "cache miss" means going all the way to RAM - much slower.

System Buses - connecting everything

Address Bus

Carries memory locations - one direction only (CPU to memory)

Data Bus

Carries actual data - bidirectional (can go both ways)

Control Bus

Carries control signals (read/write/interrupt) - bidirectional

Key registers

The registers you need to know

You do not need to know every register in a modern CPU - there are hundreds. But for GCSE, there are six that appear consistently in exam questions. Learn each one by what it holds, not just its name.

Abbreviation	Full name	What it holds	Used during
PC	Program Counter	The address of the next instruction to fetch	Fetch (increments automatically)
MAR	Memory Address Register	The address being read from or written to in RAM	Fetch (receives address from PC)
MDR	Memory Data Register	The data or instruction just fetched from (or about to be written to) RAM	Fetch and Execute (data in/out)
CIR	Current Instruction Register	The instruction currently being decoded and executed	Decode and Execute
ACC	Accumulator	The result of the most recent ALU operation	Execute
SR	Status Register	Flags indicating outcomes - overflow, carry, zero, negative	Execute (set by ALU)

Activity: Match the description

Click a register name, then click the blank to place it

MAR

MDR

CIR

ACC

ALU

1. Stores the result of a calculation:

click to fill

2. Holds the address of the next instruction:

click to fill

3. Holds the instruction being decoded right now:

click to fill

4. Performs arithmetic and logic operations:

click to fill

5. Receives the memory address from the PC during fetch:

click to fill

The system buses

Three buses - three very different jobs

Everything inside the computer communicates through three shared sets of wires called buses. Each bus carries a different type of signal, travels in a specific direction, and plays a distinct role in every single fetch-decode-execute cycle.

Address Bus

Unidirectional (CPU only)

Carries a memory address - a number that points to a specific location in RAM. The CPU places an address on this bus to say "I want whatever is stored at this location."

Because only the CPU decides what to access, data never travels back this way - it is one direction only. This is an important exam point.

The width (number of wires) determines how many locations can be addressed. A 32-bit address bus gives access to 2³² = 4,294,967,296 unique addresses (4 GB maximum). A 64-bit address bus can theoretically address 18 exabytes.

Data Bus

Bidirectional (both ways)

Carries the actual data or instructions moving between the CPU and memory (or I/O devices). It goes in both directions:

- Read: data travels from RAM to the CPU (into the MDR)
- Write: data travels from the CPU to RAM

The bus width determines how much data transfers per cycle. A 64-bit data bus moves 8 bytes simultaneously - this is why modern systems are called "64-bit."

Control Bus

Bidirectional (both ways)

Carries control signals that coordinate all components. Without it, the other two buses would carry data with no way of knowing what to do with it.

Key signals carried:

READ WRITE CLOCK INTERRUPT BUS REQUEST MEMORY SELECT

The clock signal on the control bus is what synchronises all operations to the CPU's clock speed.

Activity: Sort the statements

Click a statement, then click the bin it belongs to

Carries the instruction just fetched from RAM

Points to memory location 0x00FF42

Sends a READ signal to memory

Transfers a byte value to the MDR

Width determines max addressable RAM

Synchronises components using the clock signal

Unidirectional - travels from CPU to memory only

Signals an external device needs attention (interrupt)

Address Bus

Data Bus

Control Bus

Exam focus

Exam questions often ask you to state the direction of each bus. Learn this pattern: address bus is unidirectional (CPU to memory only). The data bus and control bus are both bidirectional. Also know: a wider address bus means more addressable memory; a wider data bus means more data transferred per cycle.

RAM and retrieval

How does the CPU actually read from RAM?

RAM (Random Access Memory) stores both the program instructions and the data being worked on. Every byte in RAM has a unique memory address - like a numbered postbox. The CPU uses addresses to find exactly the byte it needs, and the three buses carry out the request.

RAM: each cell has a unique address. Click any cell to inspect it.

Click a memory cell above to see its address and value.

RAM is called "random access" because any address can be reached in roughly the same time - you do not have to start at the beginning and read through. This is what makes it useful as working memory. The CPU can jump straight to address 0x0042 just as quickly as address 0x0001.

A memory read: step by step

When the CPU needs to fetch an instruction, this exact sequence happens. Step through it to see which register and bus is active at each point.

Memory Read Walkthrough

Fetching the instruction at address 0x00A4 - step through each stage

Step 1 of 6

Program Counter (PC)

0x00A4

Memory Address Register (MAR)

Memory Data Register (MDR)

Current Instruction Register (CIR)

→

Address Bus

←

Data Bus

←→

Control Bus

RAM

Addresses 0x00A0 - 0x00A7

0x00A0

LDA

0x00A2

ADD

0x00A4

STO 5

0x00A6

HLT

The Program Counter (PC) holds the address of the next instruction to fetch. Right now it contains 0x00A4. This is where the CPU will look in RAM.

After all six steps, the instruction is sitting in the CIR ready to be decoded. The PC has already incremented to the next address (0x00A6) so the next fetch can begin immediately. This cycle runs millions of times per second for every program that runs on any computer.

Address bus width vs maximum addressable memory:

8-bit

256 unique addresses (256 bytes max)

16-bit

65,536 addresses (64 KB max)

32-bit

4,294,967,296 addresses (4 GB max - why old systems topped out)

64-bit

18 exabytes theoretical maximum

Exam focus - memory read sequence

Know this sequence for the mark scheme: PC to MAR (address copied) → MAR to address bus (address sent to RAM) → control bus sends READ signal → RAM places data on data bus → data bus to MDR → MDR to CIR (instruction ready). PC increments throughout.

See it all in motion

The FDE Visualiser shows registers, buses and data moving between components in real time. The LMC Simulator lets you write and run simple assembly programs to see how instructions execute step by step.

FDE Visualiser LMC Simulator

Check your understanding

Lesson 2 Quiz

7 questions covering CPU, buses, and memory retrieval

Question 1 of 7

Which component of the CPU is responsible for performing arithmetic and logical comparisons?

Question 2 of 7

Which bus carries data in ONE direction only, from the CPU to memory?

Question 3 of 7

A 32-bit address bus can directly address a maximum of how much RAM?

Question 4 of 7

During a memory read, which register receives the address from the Program Counter first?

Question 5 of 7

Which bus carries the READ or WRITE signal from the CPU to memory during a fetch?

Question 6 of 7

After an instruction is fetched from RAM, where does it travel before being decoded?

Question 7 of 7

The Control Unit does not process data itself. What is its actual role in the CPU?

out of 7 correct

Think deeper

GPU (graphics processing unit) chips can contain thousands of smaller, simpler cores rather than a few fast, complex ones like a CPU. Why might this architecture be better suited to rendering graphics or training AI models?

Graphics and AI training both involve doing the same operation on millions of pieces of data at once - for example, calculating the colour of each pixel, or updating millions of neural network weights. This type of work (called data parallelism) benefits from having thousands of simple cores doing the same thing simultaneously. A CPU's small number of complex, fast cores is optimised for sequential tasks where each step depends on the result of the last - which is why CPUs excel at general computing.

Think deeper

If the data bus is bidirectional but the address bus is unidirectional, why would making the address bus bidirectional not actually help performance?

The address bus carries locations, not data. Only the CPU decides what address to access - RAM never needs to tell the CPU where to look. Making it bidirectional would add complexity and cost for no benefit, since no component other than the CPU ever needs to send an address. The direction is unidirectional by design: the CPU controls what gets fetched.

Printable Worksheets

Practice what you've learned

Three worksheets on CPU components and buses at three levels: Recall, Apply, and Exam-style.

Recall

Worksheet 1

Component matching + bus table + True/False • 18 marks

Exam-style paper including full instruction trace • 20 marks

Revision

Computer Systems Flashcards

27 key terms across all 5 lessons. Filter by topic, flip to reveal, mark as known.

Open flashcards

Lesson 1 Lesson 3: CPU Performance

Lesson 2 - Teacher Resources

Inside the CPU

Teacher mode (all pages)

Shows examiner notes on the Exam Practice page

Suggested starter (5 min)

Display a CPU diagram with all labels removed. Give students 90 seconds to write what each component is called and what it does. Collect answers - you immediately see which misconceptions exist before teaching anything. Common wrong answers: "the memory chip" for the ALU, "the brain" for everything, "the clock" for the CU. Use these as teaching moments throughout the lesson.

Lesson objectives

1Identify and describe the function of the ALU, Control Unit, and key registers (PC, MAR, MDR, ACC, CIR) and their roles during the FDE cycle.

2Explain the purpose of the three bus types - address, data, and control - describing what each carries and in which direction.

3Trace data movement through specific registers during fetch, decode, and execute phases, giving the correct register name at each step.

4Explain how bus width affects the amount of data transferred per cycle and link this to system performance.

Key vocabulary (board-ready)

ALU (Arithmetic Logic Unit)

Performs all arithmetic operations (add, subtract, multiply) and logical operations (AND, OR, NOT, comparisons). Every calculation in a program passes through the ALU.

Control Unit (CU)

Reads and decodes instructions from the CIR, then sends control signals to the ALU, registers, and buses to coordinate every stage of the FDE cycle.

Accumulator (ACC)

A register that temporarily stores the result of the most recent ALU operation, ready to be used in the next instruction or written back to memory.

Address bus

A one-way bus carrying memory addresses from the CPU to main memory or I/O devices. Its width (number of lines) determines how many unique addresses can be reached.

Data bus

A bidirectional bus carrying data and instructions between the CPU and memory. Its width determines how much data is transferred in a single cycle.

Control bus

Carries control signals from the CU to coordinate operations: read/write signals, clock pulses, interrupt requests, and bus grant signals.

Bus width

The number of parallel wires in a bus. A 64-bit data bus transfers 64 bits per cycle; a 32-bit address bus can address up to 4 GB of memory.

Suggested lesson plan

0-5 min: Starter: unlabelled CPU diagram. Students write labels and functions. Collect answers. Acknowledge what they know; highlight gaps.

5-20 min: ALU and CU: functions, differences, and how they interact during execute. Students highlight which component acts in each FDE phase.

20-35 min: Registers in detail: PC, MAR, MDR, CIR, ACC. Use the FDE Visualiser to show register values changing at each step. Pause after fetch: "Which register just updated? What does it contain?"

35-48 min: Buses: address, data, control. Direction, what is carried, width. Students calculate: if address bus = 32 bits, how much memory can be addressed? (4 GB)

48-57 min: Trace exercise: students trace a LOAD instruction through all registers from fetch to execute. Pair-check answers.

57-60 min: Exit tickets on mini-whiteboards.

Discussion prompts

The address bus is one-way (CPU to memory), but the data bus is bidirectional. Why does the direction matter? What would go wrong if you sent addresses and data on the same bus at the same time?

A 32-bit address bus can address 4 GB of memory - fine in 2000 when computers had 256 MB of RAM. Why did 32-bit systems become a problem by 2010, and what was the solution?

The ALU performs billions of operations per second but only does simple things: add, subtract, compare. How does a program as complex as a modern video game reduce to these basic operations?

Every time you press a key, dozens of CPU components activate in sequence. Starting from the electrical signal arriving, trace what happens inside the CPU before a character appears on screen.

Common misconceptions

X"The ALU does everything" - the ALU only handles arithmetic and logic. Memory access, instruction fetching, and control flow are coordinated by the CU, registers, and buses.

X"Registers are just fast RAM" - registers are built into the CPU chip, operate at full CPU speed with zero latency, and there are only a handful. They are categorically different from RAM.

X"The control bus carries data because it is bidirectional" - the control bus carries control signals (read/write, clock, interrupt). Bidirectional means signals travel both to and from devices, not that it carries program data.

X"More registers always means a faster CPU" - register count is one factor. The bottleneck is usually memory access speed or clock frequency, not register count alone.

Exit ticket questions

State the function of the ALU.

[1 mark - performs arithmetic and logical operations]

A program adds two numbers. List the CPU components involved, in order.

[3 marks - MAR/MDR fetch operands from memory / ALU performs addition / ACC stores result - accept equivalent tracing]

What determines the maximum amount of memory a CPU can address?

[1 mark - the width (number of lines) of the address bus]

Give one difference between the data bus and the control bus.

[1 mark - data bus carries data/instructions; control bus carries control signals / data bus bidirectional; any valid distinction]

Homework idea

A 32-bit system has a 32-bit address bus and 32-bit data bus. A 64-bit system doubles both. Research and write: (1) how much RAM a 32-bit system can address and why, (2) how much a 64-bit system can theoretically address, (3) one practical reason why server motherboards do not install that much RAM despite the theoretical limit.

Classroom tips

The register trace exercise is the highest-value activity in this lesson. Students who can correctly write which register holds what at each FDE step have genuinely understood the architecture.

Bus confusion is extremely common. Physical analogy: address bus = a street address (one direction, tells you where to go); data bus = a delivery van (both directions, carries content); control bus = traffic lights (signals that coordinate who moves when).

Higher students: introduce how the system clock synchronises bus operations. Every bus transfer happens on a clock edge - this connects naturally to Lesson 3.

Use the FDE Visualiser after the register introduction, not before. Let students form their mental model first, then use the visualiser to confirm or correct it.

Resources

FDE Cycle Visualiser LMC Simulator Worksheet 1 - Component matching and bus table Worksheet 2 - Register trace and bus calculations Worksheet 3 - Exam-style practice paper Computer Systems series overview Set as class homework (coming soon)