New Tool
FDE Cycle Visualiser
Watch the CPU execute a program one micro-step at a time. Animated data packets travel along colour-coded buses between every register. Every micro-operation is explained in plain English.
Address Bus
Data Bus
Control Bus
| Addr | Value | Note |
|---|
Select a program above, then press Step to begin stepping through the Fetch-Decode-Execute cycle one micro-operation at a time.
Speed:
Exam Tips
Fetch-Decode-Execute Cycle
- Fetch phase (3 steps): (1) PC contents copied to MAR via the address bus. (2) Instruction at Memory[MAR] placed into MDR via the data bus. (3) MDR contents copied to CIR. PC is then incremented by 1.
- Decode phase: The Control Unit interprets the instruction in the CIR, identifying the opcode (operation) and any operand (data address). No data moves during decode.
- Execute phase: Depends on the instruction. LDA fetches a value from memory into the ACC. STA writes the ACC value back to memory. ADD/SUB routes values through the ALU.
- Address Bus (blue): carries memory addresses from MAR to RAM. It is unidirectional -- addresses only flow from CPU to memory.
- Data Bus (green): carries data between the CPU and RAM. It is bidirectional -- instructions and data can flow either way.
- Control Bus (amber): carries control signals from the Control Unit. It coordinates all activity -- read/write signals, clock pulses, interrupt requests.
- Registers to memorise: PC (holds address of next instruction), MAR (holds address being read/written), MDR (holds data being transferred), CIR (holds current instruction being decoded), ACC (holds result of ALU operations).
- Exam question type: You may be given a table with columns for PC, MAR, MDR, CIR and ACC and asked to complete the values at each stage. Practise using this tool in Step mode.