A CPU only really does one thing, over and over, billions of times a second: fetch an instruction from memory, work out what it means, and carry it out. Below is a genuinely wired simulation, watch data actually travel along the address bus and data bus, not just a list of registers changing.
Section 2
The CPU's components
Registers are tiny, extremely fast storage locations inside the CPU, each with one specific job. The Control Unit and ALU aren't registers, but they're just as central to the cycle.
Component
Full name
Job
PC
Program Counter
Holds the address of the next instruction to fetch
MAR
Memory Address Register
Holds the address currently being read from or written to
MDR
Memory Data Register
Holds the data just fetched from (or about to be written to) memory
CIR
Current Instruction Register
Holds the instruction currently being decoded and executed
CU
Control Unit
Decodes instructions and generates the signals that coordinate every other component
ALU
Arithmetic Logic Unit
Carries out calculations (add, subtract) and comparisons
ACC
Accumulator
Holds the running result of calculations
Section 3
Watch a real program run, wire by wire
This uses the same simplified instruction set taught in Little Man Computer: LDA (load), ADD, SUB, STA (store), HLT (halt). Pick a program, then step through it, watching exactly which wire lights up at each micro-step.
Program
FETCHDECODEEXECUTEStep 0 / 0
Controls
Speed:
Address BusData BusControl signal
Ready. Pick a program and press Step to begin.
Main memory (RAM)
The general algorithm
Section 4
An instruction is just a binary number
Nothing magic is happening inside CIR: each instruction is stored as one ordinary byte, split into two halves, exactly the same idea as the number representation work you've already covered.
Instruction
Opcode (4 bits)
Meaning
HLT
0000
Stop execution
LDA n
0001
ACC ← memory[n]
ADD n
0010
ACC ← ACC + memory[n]
SUB n
0011
ACC ← ACC − memory[n]
STA n
0100
memory[n] ← ACC
Example: LDA 4 is opcode 0001 (LDA) plus operand 0100 (address 4), giving the single byte 00010100, or 0x14 in hex. The first 4 bits say what to do, the last 4 say which address.
Section 5
Addressing modes: what the operand actually means
Every LDA instruction you've run so far treated its operand as a memory address, load whatever is stored there. That's just one convention out of several, called direct addressing. The exact same operand bits, 4, can mean four completely different things depending on which addressing mode is in use, and some modes genuinely cost extra memory accesses to resolve. Step through each one and watch MAR and MDR actually do the work.
Pick a mode, then press Step to begin.
Shared memory for this demo
Index register X = 2 (used only by indexed addressing). Instruction: LDA 4.
Addressing mode
Controls
Extra memory accesses needed, beyond the instruction fetch itself
All four modes, same operand, same instruction
Exam tips
Immediate is fastest, no memory access needed at all beyond the instruction itself, but it can only ever load a fixed, hardcoded value, never something computed or looked up.
Indirect costs two extra memory accesses (read the pointer, then read the real value), the most expensive of the four here, but it's essential for things like following linked lists or passing an address around without knowing it in advance.
Indexed costs the same single extra memory access as direct, plus one addition, and is exactly how arrays work: keep the array's start address fixed in the instruction, then change the index register to walk through each element in a loop, without ever rewriting the instruction itself.
Section 6
Clock speed: how fast the cycle repeats
Clock speed, measured in Hz, is how many times per second the CPU can step through this cycle. A higher clock speed generally means more instructions completed every second.
Clock speed
Exam tips
Clock speed alone doesn't tell the whole story: number of cores (separate processing units working in parallel) and cache size (fast memory built into the CPU) both also affect real-world performance.
A single "instruction" in a real CPU can take several clock cycles, as this simulation shows: LDA, ADD, SUB and STA all need a second memory access during execute to actually read or write their operand.
Clock speed is measured in Hertz (Hz): 1 Hz is 1 cycle per second. Modern CPUs run at gigahertz (GHz), billions of cycles per second.
Section 7
Pipelining: overlapping instructions instead of queuing them
Every simulation so far has run one instruction fully to completion before starting the next: fetch, decode, execute, then fetch the next one. That's wasteful, while instruction 1 is being executed, the circuitry that does fetching is sitting completely idle. Pipelining puts it back to work immediately.
Controls
Total cycles for 4 instructions
–
Exam tips
Pipelining doesn't make any single instruction faster, each one still takes 3 cycles start to finish. What improves is throughput: how many instructions complete per unit of time, since new ones start before old ones finish.
This benefit isn't free. A branch instruction (like a jump) can force the pipeline to discard instructions it already started fetching, if the branch takes execution somewhere else entirely, all that overlapped work goes to waste, called a pipeline hazard.
Section 8
Interrupts: pausing a program without losing its place
A keyboard press, a completed disk read, a timer expiring, these all need the CPU's attention right now, even if it's halfway through something else. An interrupt is how that happens, and the entire trick is making sure the original program can resume as if nothing happened.
Controls
Saved PC register
–
where execution resumes afterward
Exam tips
The check for a pending interrupt happens at a fixed point in the cycle, typically right after execute, before the next fetch begins, never mid-instruction. An instruction that's already started is always allowed to finish.
The saved PC isn't optional, it's the entire mechanism that makes "resuming" possible at all. Without it, the CPU would have no way of knowing where the interrupted program was up to.
The Interrupt Service Routine (ISR) is just a normal, separate piece of code, stored at a known address, it runs through fetch-decode-execute exactly like anything else.